Low Power Engineer

Responsibilities:

• Work with Architecture and Product Planning team to build and own pre-silicon power modeling, power estimation and post-silicon power correlation. 
• Work closely with the Engineering team to track RTL and gate level power changes during project execution and co-ordinate with design engineers and architects to deploy low power design methods for power reduction.
• Investigate, plan, and test sub-threshold and near-threshold design methodologies and other related low power techniques for power optimization (e.g., Shared NWELL, customized standard cells, level shifters, retention flops, multi-bit flops etc.)  
• Validate and refine new low power design techniques as part of a team that is building complex test chips in advanced nodes (e.g., 12nm and beyond). 
• Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new methodologies.

Requirements:

• A master’s degree in electrical engineering or a related field is required.  
• Experience in pre-silicon power modeling, analysis, and power reduction, with proficiency in PTPX, Power Artist, or other power analysis tools and post-silicon power correlation
• Strong understanding of Low Power design methodologies, CPF/UPF, good understanding of physical design flow and timing closure with actual implementation experience as a plus.
• Experience developing new methodologies and transitioning those technologies to production is highly desirable.
• Knowledge in system architecture and SOC components such as CPU, fabric and peripherals
• Experience in system and on-die power integrity and EM would be an added advantage.
• Proficiency in scripting languages such as Shell, Perl or Python. Possess strong problem-solving and analytical skills.