Front End Central Product Integration (FE CPIE) MTS (FE)

Our client is a global technology leader specializing in advanced memory and storage solutions that power next-generation computing and data-driven applications. With strong expertise in semiconductor innovation, the organization develops high-performance memory technologies across DRAM, NAND, and storage platforms for applications spanning data centers, artificial intelligence, mobile devices, client computing, and intelligent edge ecosystems.

Driven by a commitment to technology advancement, operational excellence, and customer-centric innovation, the company plays a significant role in enabling modern digital infrastructure and compute-intensive workloads worldwide.

Responsibilities:

• Lead process integration (PI) structural uniformity and cross loop integration for critical modules (e.g., capacitance loop), owning end to end integration strategies to resolve yield, quality, and reliability gaps.
• Drive physics and process based integration solutions through close collaboration with cross module process owners, PI subject matter experts, and key suppliers to optimise integration structures and achieve BIC yield and quality targets.
• Develop and apply model based root cause analysis frameworks (transport, reaction kinetics, pattern density, and geometry dependent effects) to diagnose structural non uniformity. Define, implement, and continuously strengthen critical inline monitoring and defence lines (CD, film loss, mass delta, defectivity, edge/periphery metrics) to ensure robust control of structural uniformity.
• Own and advance product integration programs and loop level domain expertise, maintaining deep technical knowledge across node transitions.
• Proactively drive node over node “shift left” integration, including early implementation of uniformity, bevel, and backside best known methods (BKMs) during development phases to accelerate whole wafer (centre-to-edge) yield and quality ramp.
• Drive worldwide technical alignment and execution excellence by leading global projects, standardizing and leveraging network BKMs, and scaling proven solutions across sites. Identify efficiency and performance gaps, and lead business process creation, optimization, and re engineering to improve benchmark performance, cycle time, and development productivity.
• Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements.

Requirements:

• Bachelor's/Master's/PhD. in EE, Materials Engineering, Materials Science, Physics and Chemical but optional if candidates have more than 10 years' experience in process related role in the semiconductor industry.
• With more than 7 years of relevant industry experience/knowledges.
• Good logical thinking and knowledge in Semiconductor Fabrication process flows, interaction of different processes and how changes affect yield, device performance and reliability. Understanding of DRAM and NAND operation and structure to decipher parametric, probe and qual data from both front-end and backend assembly processes.
• Good model-based problem solving, together with data-driven decision making, and presentation skills. Proven ability to troubleshoot and solve structure and device-related issues, and address root cause.
• Good organizational capabilities and ability to work effectively. Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities. Travel to company sites as necessary for face-to-face collaboration.
• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.
• Good multi-tasking, verbal and written communication skills.
• Ability to apply baseline digital fluency and role appropriate AI literacy to use AI enabled tools responsibly and effectively for research, analysis, content creation, problem solving, operational tasks, and achieving business outcomes