Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering

Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

Responsibilities: <ul><li>Develop wafer-level process technologies including wafer thinning and backside metal interconnect.</li><li>Improve process capability, yield, and manufacturing cost.</li><li>Establish process management projects supporting future technology nodes.</li><li>Evaluate, qualify, and implement new equipment and materials.</li><li>Set process parameters for semiconductor manufacturing equipment.</li><li>Drive process quality through inspection, testing, measurement, SPC, DOE, and defect analysis.</li><li>Develop advanced process controls using data analytics.</li><li>Collaborate with Package Integration, Assembly Engineering, Front-End Wafer Fab, Product Engineering, Assembly/Test Engineering, and Global Quality teams.</li><li>Support product transfer from development through qualification to High Volume Manufacturing (HVM).</li><li>Provide Process of Record (POR) and Model of Record (MOR) documentation</li></ul> Requirements: <ul><li>B.S./M.S./Ph.D. (or equivalent) in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or related technical discipline.</li><li>2+ years of semiconductor process development experience, preferably in wafer bonding, plating, warpage control, or advanced packaging.</li><li>Proficiency in Python, R, and SQL.</li><li>Experience with Visual Basic.</li><li>Knowledge of E3, FDC (Fault Detection &amp; Classification), and RMS (Recipe Management System).</li><li>Strong statistical analysis, process modeling, SPC, DOE, and dashboard development skills.</li><li>Strong understanding of semiconductor process interactions, yield, performance, and reliability.</li><li>Excellent problem-solving and root-cause analysis capability.</li><li>Ability to deliver results under aggressive timelines and limited resources.</li></ul>

Responsibilities: <ul><li>Develop and enable advanced package technologies for post-fab wafer finish and assembly processes.</li><li>Improve product quality, yield, productivity, and manufacturing cost.</li><li>Partner with process and product engineering teams to integrate semiconductor technologies.</li><li>Drive yield improvements through package integration innovation, layout optimization, design improvements, and process margin enhancement.</li><li>Collect and analyze data to support design, layout, and integration flow decisions.</li><li>Collaborate with Probe, Yield Analysis, Test, Product Engineering, PWF Engineering, Assembly Engineering, Front-End Wafer Fab, Assembly/Test Engineering, and Global Quality teams.</li><li>Ensure robust quality through process monitoring, inspection, testing, SPC, DOE, and defect analysis.</li><li>Support product transition from development through qualification into High Volume Manufacturing (HVM).</li><li>Provide Process of Record (POR) and Model of Record (MOR) documentation.</li></ul> Requirements: <ul><li>B.S./M.S./Ph.D. (or equivalent) in Electrical, Mechanical, Chemical Engineering, Physics, Materials Science, or related discipline.</li><li>2+ years of semiconductor process integration experience, preferably in advanced packaging, post-fab wafer finishing, or assembly processes.</li><li>Proficiency in Python, R, and SQL.</li><li>Experience with Visual Basic.</li><li>Knowledge of E3, FDC, and RMS (Recipe Management System).</li><li>Strong statistical analysis, process modeling, SPC, DOE, defect analysis, and dashboarding skills.</li><li>Strong understanding of semiconductor process flows and integration.</li><li>Strong root-cause analysis and complex problem-solving capability.</li><li>Ability to work under tight timelines and limited resources.</li></ul>

Responsibilities: <ul><li>Develop and optimize assembly processes for advanced packaging technologies, including wafer-level packaging, Chip-on-Wafer (CoW), and Chip-to-Wafer (C2W) die stacking.</li><li>Improve product quality, yield, productivity, and manufacturing cost.</li><li>Drive process management projects supporting future technology nodes.</li><li>Evaluate, qualify, and implement new equipment and materials.</li><li>Establish process parameters for semiconductor manufacturing equipment.</li><li>Ensure robust quality through process monitoring, inspection, testing, SPC, DOE, and defect analysis.</li><li>Use data analytics to establish advanced process controls and identify improvement opportunities.</li><li>Collaborate with Package Integration, Assembly Engineering, Front-End Wafer Fab, Assembly/Test Engineering, Product Engineering, and Global Quality teams.</li><li>Support seamless transition from product development through qualification into High Volume Manufacturing (HVM).</li><li>Provide Process of Record (POR) and Model of Record (MOR) documentation.</li></ul> Requirements: <ul><li>B.S./M.S./Ph.D. (or equivalent) in Materials Science, Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or related technical discipline.</li><li>2+ years of semiconductor process development or equipment evaluation experience, preferably in wafer bonding, die stacking, or advanced packaging.</li><li>Proficiency in Python, R, and SQL.</li><li>Experience with Visual Basic for automation and tool integration.</li><li>Knowledge of E3, FDC (Fault Detection and Classification), and RMS (Recipe Management System).</li><li>Strong data analytics capability supporting SPC, DOE, defect analysis, and dashboards.</li><li>Strong understanding of semiconductor process flows, yield, performance, and reliability.</li><li>Strong problem-solving and root-cause analysis skills.</li><li>Ability to work effectively under aggressive timelines and limited resources.</li></ul>

Responsibilities: <ul><li>Develop wafer-level process technologies including wafer thinning and backside metal interconnect.</li><li>Improve process capability, yield, and manufacturing cost.</li><li>Establish process management projects supporting future technology nodes.</li><li>Evaluate, qualify, and implement new equipment and materials.</li><li>Set process parameters for semiconductor manufacturing equipment.</li><li>Drive process quality through inspection, testing, measurement, SPC, DOE, and defect analysis.</li><li>Develop advanced process controls using data analytics.</li><li>Collaborate with Package Integration, Assembly Engineering, Front-End Wafer Fab, Product Engineering, Assembly/Test Engineering, and Global Quality teams.</li><li>Support product transfer from development through qualification to High Volume Manufacturing (HVM).</li><li>Provide Process of Record (POR) and Model of Record (MOR) documentation.</li></ul> Requirements: <ul><li>B.S./M.S./Ph.D. (or equivalent) in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Physics, or related technical discipline.</li><li>2+ years of semiconductor process development experience, preferably in wafer bonding, plating, warpage control, or advanced packaging.</li><li>Proficiency in Python, R, and SQL.</li><li>Experience with Visual Basic.</li><li>Knowledge of E3, FDC (Fault Detection &amp; Classification), and RMS (Recipe Management System).</li><li>Strong statistical analysis, process modeling, SPC, DOE, and dashboard development skills.</li><li>Strong understanding of semiconductor process interactions, yield, performance, and reliability.</li><li>Excellent problem-solving and root-cause analysis capability.</li><li>Ability to deliver results under aggressive timelines and limited resources.</li></ul>

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6 rms Jobs found

Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering

Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering

Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

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6 rms Jobs found

Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering

Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

Principal/Senior Engineer, APTD CEM - Advanced Packaging Integration Engineering

Principal/Staff/Senior Engineer, APTD CEM - Advanced Packaging Wafer Level Technology Engineering

Senior Engineer, APTD CEM - Advanced Packaging Die Level Technology Engineering

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