DFT Engineer

FPGA Engineer

Low Power Engineer

Responsibilities: <ul><li>Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.</li><li>Develop and implement low-power DFT architecture and infrastructure.</li><li>Generate structural test vectors, analyze and improve coverage, test time and test cost.</li><li>Perform pre/post-layout scan and MBIST simulations.</li><li>Work with designers on STA, physical, power and logical issues related to DFT.</li><li>Work with test engineers to bring up test vectors on silicon.</li></ul> Requirements: BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.Experience in creating and implementing hierarchical DFT architecture in complex SoC.Experience in Low-Power DFT and MBIST.Experience in test time and test coverage analysis for scan and MBIST patterns.Experience with working with test engineering team to bring up production test program.Extensive knowledge of timing concepts and constraint development.Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.Experience in RTL is required.Experience in scripting like is preferred.

Responsibilities:&nbsp; <ul><li>Work with software and design teams to understand the functional and performance goals of MCU design.</li><li>Follow the FPGA/Emulation process flow and platforms across multiple pre-silicon design projects while working with Emulation team members across multiple geographies.</li><li>Implement and debug FPGA design primarily on Stratix-10 development board using Quartus.</li><li>Assist software and validation teams in reproduction, triage, and debug of issues.</li><li>Support a regression test suite consisting of system-level test cases to validate updated FPGA builds.&nbsp;&nbsp;</li></ul> Requirements: <ul><li>BSEE or BSCE with 5+ years of SoC design, verification, or related work experience and 2+ years of experience of FPGA design, bring-up, debugging, and verification;&nbsp;&nbsp;</li><li>In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on a platform comprising one FPGA;</li><li>Expertise in Intel Quartus Prime Pro or Xilinx Vivado suites with emphasis on Quartus Prime Pro 19.x and later;&nbsp;&nbsp;</li><li>Solid understanding of the tool flow from RTL to bitstream;</li><li>In-depth experience writing Verilog code and FPGA timing analysis;</li><li>Familiarity with source code control systems (git) required;</li><li>Familiarity with languages such as C/C++, Make, TCL, Python script is a plus;&nbsp;</li><li>Familiarity with embedded systems and interfaces such as I2C, SPI, MSPI, UART, USB, SDIO, MIPI is a plus.</li></ul>

Responsibilities: <ul><li>Work with Architecture and Product Planning team to build and own pre-silicon power modeling, power estimation and post-silicon power correlation.&nbsp;</li><li>Work closely with the Engineering team to track RTL and gate level power changes during project execution and co-ordinate with design engineers and architects to deploy low power design methods for power reduction.</li><li>Investigate, plan, and test sub-threshold and near-threshold design methodologies and other related low power techniques for power optimization (e.g., Shared NWELL, customized standard cells, level shifters, retention flops, multi-bit flops etc.)&nbsp;&nbsp;</li><li>Validate and refine new low power design techniques as part of a team that is building complex test chips in advanced nodes (e.g., 12nm and beyond).&nbsp;</li><li>Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new methodologies.</li></ul> Requirements: <ul><li>A master’s degree in electrical engineering or a related field is required.&nbsp;&nbsp;</li><li>Experience in pre-silicon power modeling, analysis, and power reduction, with proficiency in PTPX, Power Artist, or other power analysis tools and post-silicon power correlation</li><li>Strong understanding of Low Power design methodologies, CPF/UPF, good understanding of physical design flow and timing closure with actual implementation experience as a plus.</li><li>Experience developing new methodologies and transitioning those technologies to production is highly desirable.</li><li>Knowledge in system architecture and SOC components such as CPU, fabric and peripherals</li><li>Experience in system and on-die power integrity and EM would be an added advantage.</li><li>Proficiency in scripting languages such as Shell, Perl or Python. Possess strong problem-solving and analytical skills.</li></ul>

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DFT Engineer

FPGA Engineer

Low Power Engineer

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DFT Engineer

FPGA Engineer

Low Power Engineer

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