DFT Engineer

FPGA Engineer

Responsibilities: <ul><li>Responsible for scan insertion, boundary scan, MBIST, ATPG for ultra-low power SoC based on subthreshold operation using standard EDA tools.</li><li>Develop and implement low-power DFT architecture and infrastructure.</li><li>Generate structural test vectors, analyze and improve coverage, test time and test cost.</li><li>Perform pre/post-layout scan and MBIST simulations.</li><li>Work with designers on STA, physical, power and logical issues related to DFT.</li><li>Work with test engineers to bring up test vectors on silicon.</li></ul> Requirements: BS/MS in ECE/EE and at least 10 years of experience in DFT implementation.Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST.Experience in creating and implementing hierarchical DFT architecture in complex SoC.Experience in Low-Power DFT and MBIST.Experience in test time and test coverage analysis for scan and MBIST patterns.Experience with working with test engineering team to bring up production test program.Extensive knowledge of timing concepts and constraint development.Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments.Experience in RTL is required.Experience in scripting like is preferred.

Responsibilities:&nbsp; <ul><li>Work with software and design teams to understand the functional and performance goals of MCU design.</li><li>Follow the FPGA/Emulation process flow and platforms across multiple pre-silicon design projects while working with Emulation team members across multiple geographies.</li><li>Implement and debug FPGA design primarily on Stratix-10 development board using Quartus.</li><li>Assist software and validation teams in reproduction, triage, and debug of issues.</li><li>Support a regression test suite consisting of system-level test cases to validate updated FPGA builds.&nbsp;&nbsp;</li></ul> Requirements: <ul><li>BSEE or BSCE with 5+ years of SoC design, verification, or related work experience and 2+ years of experience of FPGA design, bring-up, debugging, and verification;&nbsp;&nbsp;</li><li>In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on a platform comprising one FPGA;</li><li>Expertise in Intel Quartus Prime Pro or Xilinx Vivado suites with emphasis on Quartus Prime Pro 19.x and later;&nbsp;&nbsp;</li><li>Solid understanding of the tool flow from RTL to bitstream;</li><li>In-depth experience writing Verilog code and FPGA timing analysis;</li><li>Familiarity with source code control systems (git) required;</li><li>Familiarity with languages such as C/C++, Make, TCL, Python script is a plus;&nbsp;</li><li>Familiarity with embedded systems and interfaces such as I2C, SPI, MSPI, UART, USB, SDIO, MIPI is a plus.</li></ul>

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DFT Engineer

FPGA Engineer

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DFT Engineer

FPGA Engineer

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